Memory devices find ubiquitous use in electronic devices, such as in consumer electronics. Memory devices are typically used to store executable code and data for the runtime operation of the electronic device. Many electronic devices stay operating almost continuously for long periods of time, potentially transferring large amounts of data in and out of the memory devices. Thus, it is important that the memory devices perform according to design expectations. However, memory devices are subject to failure from design issues or manufacturing inconsistencies. The failures can show up right after manufacturing as well as in operation of the devices.
Memory testing is used to detect abnormalities or other unexpected behavior in the memory devices. Some errors relate to the operation of the memory subsystem with respect to storing and transferring data. Other errors relate to the operation of the memory subsystem with respect to commands. Errors related to memory device commands are more difficult to test, due to a greater difficulty in creating conditions to create the errors in command processing by the memory device.
Creating high-stress command bus patterns can be difficult due to the need to maintain protocol compliance. Test data for the data bus can be of any value, making it fairly straightforward to generate a wide variety of high stress patterns. In contrast, the command bus has restrictions on the values that can be assigned to the individual lanes of the command bus. The protocol requirements of the different command bus lanes means that an attempt to drive random values to the memory device will likely violate a memory device signaling/interconnection protocol, resulting in an error (e.g., reading from a location that has not yet been activated).
Thus, traditional memory subsystem tests could not create data with sufficiently high-stress patterns on the command bus. Among other missing testing capabilities, traditional tests have been unable to control patterns during various cycles of the command bus. Additionally, there have been problems trying to synchronize or integrate test data with real data on the command bus.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.